This invention relates, in general, to integrated circuit protection structures, and more particularly to an electro-static discharge (ESD) structure for protecting integrated circuits from extreme ESD conditions and a method of manufacture.
ESD is a well-known and documented problem in integrated circuit (IC) manufacturing and usage. ESD occurs when large voltage pulses from static electricity are applied to the I/O pads of integrated circuits. ESD voltage spikes may cause damage to insulating layers and conductive interconnects and integrated semiconductor devices, which can result in short and/or open circuit failures and overheating. Additionally, such spikes can damage junction regions causing cross diffusion and melting.
ESD protection has emerged as a major design challenge in certain high frequency applications such as radio frequency (RF), digital, and mixed signal integrated circuits. For all IC applications, higher failure voltages and smaller available areas for placing an ESD structure on an IC are driving factors for ESD performance levels. In addition, an ESD load often dominates the parasitic capacitance, which becomes a significant problem at higher operating frequencies. ESD device related parasitic capacitance slows signals down, causes large reflections, and limits chip-to-chip signal bandwidth. As a result, a significant part of a signal may be lost through ESD circuits, which makes them a major obstacle for high-speed operation.
Some industries, such as the automotive, computing, and personal communication industries, now require ESD testing and certification up to 20 kV, which puts higher demands and stresses on ESD structures. In particular, such stresses are troublesome in IC technologies incorporating bump structures on I/O pads where such stresses can lead to device degradation or failure.
Accordingly, ESD structures and methods are needed that can withstand ≧15 kV air and contact discharge events, and that have mechanical robustness and long-term reliability. Additionally, it would be advantageous for such structures and methods to be easily integrated into typical IC process flows, to have reduced parasitic effects particularly for high frequency applications, and to take-up minimal space.
For ease of understanding, elements in the drawing figures are not necessarily drawn to scale, and like element numbers are used where appropriate throughout the various figures. Additionally, the terms first, second, third, and the like in the description and claims, if any, are used for distinguishing between elements and not necessarily for describing sequential or chronological order. It is understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences that are described or illustrated herein.